As devices have been scaled, the channel length in the semiconductor devices has become smaller and smaller. When the semiconductor devices have a gate size of 0.30 .mu.m, for example, the extremely short channel length generates a hot carrier effect. For example, as the channel length is made smaller, its associated electric field increases. As the electric field increases, the force on the electrons increases causing them to move faster and faster in the channel. Such energetic electrons are referred to as "hot carriers".
There is a potential barrier between the silicon substrate and the silicon dioxide (SiO.sub.2) gate oxide of a metal oxide semiconductor (MOS) transistor. As electrons flow in the channel, some scattering of the electrons in the lattice of the silicon substrate occurs due to interface states and fixed charges (interface defects). As electron scattering increases, the mobility of the hot carriers is reduced, thereby reducing the current flowing through the channel. Over a period of time, hot carriers degrade the silicon bonds with an attendant increase in electron scattering due to an increase in interface and bulk defects. As a result, the transistor slows down over a period of time. The lifetime of the transistor is normally measured as the length of time a device operates until a 10% degradation in the operation of the device is reached. This may be measured, for example, as a 10% reduction in the current flow in the channel. For example, if a transistor designed for a 10 milliamp current in 3.3 volt technology is reduced to less than 9 milliamp within one year, the semiconductor device is said to have a hot carrier lifetime of one year. The hot carrier lifetime constraints in an NMOS device limits the current drive that can be used in a given technology. By improving the hot carrier lifetime, the current drive can be increased, thereby increasing the operating speed of a device, such as a microprocessor.
A conventional method for manufacturing semiconductor devices involves local interconnect technology wherein through-holes are etched through a dielectric layer to the active device regions on a semiconductor substrate. The through-holes are filled with a conductive material for electrical to the device regions. This technique is favored due to the reduction in the number of metallization layers made possible by the local interconnection of the device regions.
In conventional local interconnect methodology, the through-holes are formed by etching through a dielectric material, such as spin on glass (SOG), tetraethylorthosilicate (TEOS) or a high density plasma oxide. The through-holes are etched to eventually expose at least one of the gate electrode, drain and/or source of the transistor. It is critically important for proper functioning operation of the final semiconductor device that such through-hole etching is performed carefully such that the underlying conductive layer or regions, e.g., a metal silicide layer on the upper surface of the gate, drain and/or source, and the gate polysilicon and/or the doped source/drain regions in the substrate. However, the distance of the through-hole between the upper surfaces of the dielectric layer and the gate electrode is shorter than the distance of the through-holes to the source/drain regions to the upper surface of the dielectric layer. When etching through the dielectric layer, the through-hole to the gate is completed well before the through-hole to the source/drain regions. If etching is not controlled, over-etching through the gate electrode would occur before the through-holes are extended to the source/drain regions. A conventional approach to this problem resides in depositing an etch stop layer to halt the through-hole etching upon reaching the gate electrode, allowing the etching of through holes to the source/drain regions to continue.
In the conventional local interconnect process, silicon nitride (Si.sub.3 N.sub.4) is the preferred etch stop layer when etching through an overlying oxide layer, due to its excellent etch selectivity with respect to silicon dioxide and to the metal silicide layers forming contacts to the gate electrode and source/drain regions. Once the first etching process is completed, so that the through-holes extend to the silicon nitride etch stop layer, a second etching technique is performed to etch through the silicon nitride etch stop layer to the metal silicide contact layers on the gate electrode, and source/drain regions.
Semiconductor devices produced by such conventional local interconnect methodology have relatively short hot carrier lifetimes. After experimentation and investigation, it was found that the use of the silicon nitride as the etch stop layer in the conventional local interconnect method reduces the lifetime of the device. The exact mechanism involved such lifetime lowering is not known. However, it is believed that the silicon nitride etch stop layer somehow degrades the silicon dioxide/silicon substrate interface, thereby lowering the lifetime of the resulting semiconductor device.